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» Design and Implementation of the TRIPS Primary Memory System
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STTT
2010
115views more  STTT 2010»
14 years 10 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
HPCA
2011
IEEE
14 years 3 months ago
Calvin: Deterministic or not? Free will to choose
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
Derek Hower, Polina Dudnik, Mark D. Hill, David A....
ASPLOS
2011
ACM
14 years 3 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
EUROSYS
2009
ACM
15 years 9 months ago
xCalls: safe I/O in memory transactions
Memory transactions, similar to database transactions, allow a programmer to focus on the logic of their program and let the system ensure that transactions are atomic and isolate...
Haris Volos, Andres Jaan Tack, Neelam Goyal, Micha...
ASPLOS
1992
ACM
15 years 3 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta