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» Design and Implementation of the TRIPS Primary Memory System
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ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
ASPLOS
2006
ACM
15 years 5 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
HPCA
1998
IEEE
15 years 4 months ago
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
Sujoy Basu, Josep Torrellas
ISCAS
2008
IEEE
85views Hardware» more  ISCAS 2008»
15 years 6 months ago
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder
High Definition (HD) H.264/AVC video compression is the emerging necessity on nowadays home entertainment environment and so on. However, Although B-frame coding scheme provides ...
Yi-Hau Chen, Tzu-Der Chuang, Yu-Han Chen, Chen-Han...
ISCA
2007
IEEE
198views Hardware» more  ISCA 2007»
15 years 6 months ago
Making the fast case common and the uncommon case simple in unbounded transactional memory
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
Colin Blundell, Joe Devietti, E. Christopher Lewis...