862 search results - page 89 / 173 » Design and Implementation of the TRIPS Primary Memory System |
102
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ASAP
2006
IEEE
15 years 1 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
120
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OSDI
2002
ACM
16 years 4 days ago
2002
ACM
Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a...
111
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RTS
2008
14 years 11 months ago
2008
Dynamic memory allocation has been used for decades. However, it has seldom been used in real-time systems since the worst case of spatial and temporal requirements for allocation ...
101
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DSL
1997
15 years 1 months ago
1997
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
100
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FTCS
1996
15 years 1 months ago
1996
This paper presents a benchmark for dependablesystems. The benchmark consists of two metrics, number of catastrophic incidents and performance degradation, which are obtained by a...