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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ICSE
1999
IEEE-ACM
15 years 2 months ago
Using a Goal-Driven Approach to Generate Test Cases for GUIs
The widespread use of GUIs for interacting with software is leading to the construction of more and more complex GUIs. With the growing complexity comes challenges in testing the ...
Atif M. Memon, Martha E. Pollack, Mary Lou Soffa
WSC
1998
14 years 11 months ago
Applying Temporal Databases to HLA Data Collection and Analysis
The High Level Architecture (HLA) for distributed simulations was proposed by the Defense Modeling and Simulation Office of the Department of Defense (DOD) in order to support int...
Thom McLean, Leo Mark, Margaret L. Loper, David Ro...
BMCBI
2006
99views more  BMCBI 2006»
14 years 9 months ago
MAGIC-SPP: a database-driven DNA sequence processing package with associated management tools
Background: Processing raw DNA sequence data is an especially challenging task for relatively small laboratories and core facilities that produce as many as 5000 or more DNA seque...
Chun Liang, Feng Sun, Haiming Wang, Junfeng Qu, Ro...
BMCBI
2006
131views more  BMCBI 2006»
14 years 9 months ago
The statistics of identifying differentially expressed genes in Expresso and TM4: a comparison
Background: Analysis of DNA microarray data takes as input spot intensity measurements from scanner software and returns differential expression of genes between two conditions, t...
Allan A. Sioson, Shrinivasrao P. Mane, Pinghua Li,...
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