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» Design and Performance of Optimized Relay Mappings
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CGO
2007
IEEE
15 years 4 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
IROS
2007
IEEE
193views Robotics» more  IROS 2007»
15 years 4 months ago
Analyzing gaussian proposal distributions for mapping with rao-blackwellized particle filters
Abstract— Particle filters are a frequently used filtering technique in the robotics community. They have been successfully applied to problems such as localization, mapping, o...
Cyrill Stachniss, Giorgio Grisetti, Wolfram Burgar...
FPL
2006
Springer
113views Hardware» more  FPL 2006»
15 years 1 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 2 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
15 years 3 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...