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» Design and Performance of Optimized Relay Mappings
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FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
15 years 1 months ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich
SIGMOD
2011
ACM
210views Database» more  SIGMOD 2011»
14 years 17 days ago
A platform for scalable one-pass analytics using MapReduce
Today’s one-pass analytics applications tend to be data-intensive in nature and require the ability to process high volumes of data efficiently. MapReduce is a popular programm...
Boduo Li, Edward Mazur, Yanlei Diao, Andrew McGreg...
HPDC
2010
IEEE
14 years 10 months ago
Multi-GPU volume rendering using MapReduce
In this paper we present a multi-GPU parallel volume rendering implemention built using the MapReduce programming model. We give implementation details of the library, including s...
Jeff A. Stuart, Cheng-Kai Chen, Kwan-Liu Ma, John ...
C3S2E
2009
ACM
15 years 1 months ago
The promise of solid state disks: increasing efficiency and reducing cost of DBMS processing
Most database systems (DBMSs) today are operating on servers equipped with magnetic disks. In our contribution, we want to motivate the use of two emerging and striking technologi...
Karsten Schmidt 0002, Yi Ou, Theo Härder
CODES
2008
IEEE
14 years 11 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...