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» Design and Performance of Optimized Relay Mappings
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FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
15 years 4 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 6 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
DATE
2004
IEEE
118views Hardware» more  DATE 2004»
15 years 1 months ago
Distributed Multimedia System Design: A Holistic Perspective
Multimedia systems play a central part in many human activities. Due to the significant advances in the VLSI technology, there is an increasing demand for portable multimedia appl...
Radu Marculescu, Massoud Pedram, Jörg Henkel
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
15 years 2 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 6 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He