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» Design and Performance of Optimized Relay Mappings
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ICC
2007
IEEE
164views Communications» more  ICC 2007»
15 years 6 months ago
An Application-Driven Mobility Management Scheme for Hierarchical Mobile IPv6 Networks
— Mobile users are expected to be highly dynamic in next generation mobile networks. Additionally they will be served a wide variety of services with different transmission rates...
Tarik Taleb, Yuji Ikeda, Kazuo Hashimoto, Yoshiaki...
IPPS
2009
IEEE
15 years 6 months ago
Multi-dimensional characterization of temporal data mining on graphics processors
Through the algorthmic design patterns of data parallelism and task parallelism, the graphics processing unit (GPU) offers the potential to vastly accelerate discovery and innovat...
Jeremy S. Archuleta, Yong Cao, Thomas Scogland, Wu...
DAC
2006
ACM
16 years 23 days ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 3 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
CASES
2003
ACM
15 years 5 months ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara