330 search results - page 44 / 66 » Design and Performance of Optimized Relay Mappings |
HICSS
2006
IEEE
15 years 3 months ago
2006
IEEE
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
DAC
2010
ACM
15 years 1 months ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
GLOBECOM
2006
IEEE
15 years 3 months ago
2006
IEEE
We consider a MIMO system where error-prone feedback from the receiver is used by the transmitter to select a single optimum antenna to transmit data. Such error-prone feedback is...