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» Design and Performance of Optimized Relay Mappings
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FPL
2005
Springer
115views Hardware» more  FPL 2005»
15 years 3 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
TON
2008
107views more  TON 2008»
14 years 9 months ago
Efficient routing in intermittently connected mobile networks: the multiple-copy case
Abstract--Intermittently connected mobile networks are wireless networks where most of the time there does not exist a complete path from the source to the destination. There are m...
Thrasyvoulos Spyropoulos, Konstantinos Psounis, Ca...
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
15 years 1 months ago
Fast Comparisons of Circuit Implementations
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
Shrirang K. Karandikar, Sachin S. Sapatnekar
TASLP
2002
110views more  TASLP 2002»
14 years 9 months ago
Automatic generation of subword units for speech recognition systems
Large vocabulary continuous speech recognition (LVCSR) systems traditionally represent words in terms of smaller subword units. Both during training and during recognition, they re...
Rita Singh, Bhiksha Raj, Richard M. Stern
ERSA
2004
129views Hardware» more  ERSA 2004»
14 years 11 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna