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» Design and Performance of Optimized Relay Mappings
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VLSISP
2008
104views more  VLSISP 2008»
14 years 9 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
DAC
2009
ACM
15 years 10 months ago
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
CODES
2002
IEEE
15 years 2 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
JPDC
2011
219views more  JPDC 2011»
14 years 4 months ago
BlobSeer: Next-generation data management for large scale infrastructures
As data volumes increase at a high speed in more and more application fields of science, engineering, information services, etc., the challenges posed by data-intensive computing...
Bogdan Nicolae, Gabriel Antoniu, Luc Bougé,...
IPPS
2002
IEEE
15 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...