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» Design and Performance of Optimized Relay Mappings
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IPPS
2006
IEEE
15 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
TMC
2010
100views more  TMC 2010»
14 years 8 months ago
Optimal Relay Station Placement in Broadband Wireless Access Networks
—To satisfy the stringent requirement of capacity enhancement in wireless networks, cooperative relaying is envisioned as one of the most effective solutions. In this paper, we s...
Bin Lin, Pin-Han Ho, Liang-Liang Xie, Xuemin (Sher...
CORR
2008
Springer
125views Education» more  CORR 2008»
14 years 9 months ago
Cross-Layer Link Adaptation Design for Relay Channels with Cooperative ARQ Protocol
The cooperative automatic repeat request (C-ARQ) is a link layer relaying protocol which exploits the spatial diversity and allows the relay node to retransmit the source data pac...
Morteza Mardani, Jalil S. Harsini, Farshad Lahouti
83
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WCNC
2010
IEEE
14 years 8 months ago
Robust Relay Precoder Design for MIMO-Relay Networks
Abstract—In this paper, we consider a robust design of MIMOrelay precoder and receive filter for the destination nodes in a non-regenerative multiple-input multiple-output (MIMO...
P. Ubaidulla, Ananthanarayanan Chockalingam
DAC
2006
ACM
15 years 10 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong