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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 4 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
DAC
2008
ACM
15 years 10 months ago
Functional test selection based on unsupervised support vector analysis
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Fo...
CODES
1999
IEEE
15 years 2 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
ICSE
2011
IEEE-ACM
14 years 1 months ago
Leveraging software architectures to guide and verify the development of sense/compute/control applications
A software architecture describes the structure of a computing system by specifying software components and their interactions. Mapping a software architecture to an implementatio...
Damien Cassou, Emilie Balland, Charles Consel, Jul...
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DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 3 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas