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ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 6 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
CGO
2010
IEEE
15 years 6 months ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the dif...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...
JSA
2010
173views more  JSA 2010»
14 years 8 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
ANCS
2007
ACM
15 years 5 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
SACMAT
2011
ACM
14 years 4 months ago
An integrated approach for identity and access management in a SOA context
In this paper, we present an approach for identity and access management (IAM) in the context of (cross-organizational) serviceoriented architectures (SOA). In particular, we de...
Waldemar Hummer, Patrick Gaubatz, Mark Strembeck, ...