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FCCM
1998
IEEE
119views VLSI» more  FCCM 1998»
15 years 2 months ago
Specifying and Compiling Applications for RaPiD
E cient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that...
Darren C. Cronquist, Paul Franklin, Stefan G. Berg...
EUROPAR
2008
Springer
14 years 11 months ago
Parallel Lattice Boltzmann Flow Simulation on Emerging Multi-core Platforms
Abstract. A parallel Lattice Boltzmann Method (pLBM), which is based on hierarchical spatial decomposition, is designed to perform large-scale flow simulations. The algorithm uses ...
Liu Peng, Ken-ichi Nomura, Takehiro Oyakawa, Rajiv...
DAC
2011
ACM
13 years 9 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
15 years 10 months ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
VLSID
2006
IEEE
71views VLSI» more  VLSID 2006»
15 years 3 months ago
Clockless Pipelining for Coarse Grain Datapaths
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Abdelhalim Alsharqawi, Abdel Ejnioui