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» Design and architectures for dependable embedded systems
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CODES
2006
IEEE
15 years 9 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
IPPS
1999
IEEE
15 years 9 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
IWCMC
2010
ACM
15 years 10 months ago
Turbo packet combining techniques for multi-relay-assisted systems over multi-antenna broadband channels
This paper focuses on turbo packet combining techniques for multi-relay-assisted systems operating over multiple-input multiple-output (MIMO) broadband channel. Two packet combini...
Houda Chafnaji, Halim Yanikomeroglu, Tarik Ait-Idi...
JCM
2008
101views more  JCM 2008»
15 years 5 months ago
MIMO Channel Sounder at 3.5 GHz: Application to WiMAX System
The use of antenna arrays at emission and reception seems to represent a prominent solution for future wireless systems, it improves data rates and enhances the quality of service....
Hanna Farhat, Guy Grunfelder, Alvaro Carcelen, Gha...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 11 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy