620 search results - page 117 / 124 » Design and evaluation of an auto-memoization processor |
MICRO
2008
IEEE
15 years 6 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
102
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ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
IEEEPACT
2006
IEEE
15 years 5 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
98
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EGH
2004
Springer
15 years 5 months ago
2004
Springer
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
116
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ICS
2004
Tsinghua U.
15 years 5 months ago
2004
Tsinghua U.
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...