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» Design and implementation of a low-power workstation
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ICCAD
2002
IEEE
92views Hardware» more  ICCAD 2002»
15 years 6 months ago
Optimization of a fully integrated low power CMOS GPS receiver
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
Peter J. Vancorenland, Philippe Coppejans, Wouter ...
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 3 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ISLPED
1999
ACM
160views Hardware» more  ISLPED 1999»
15 years 1 months ago
Mixed-swing quadrail for low power dual-rail domino logic
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
Bharath Ramasubramanian, Herman Schmit, L. Richard...
CF
2008
ACM
14 years 11 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
69
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VLSID
2007
IEEE
128views VLSI» more  VLSID 2007»
15 years 10 months ago
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj...