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» Design and implementation of a low-power workstation
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ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
15 years 6 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
TVLSI
2010
14 years 4 months ago
Low-Power Multimedia System Design by Aggressive Voltage Scaling
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanle...
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
15 years 10 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
AES
2004
Springer
190views Cryptology» more  AES 2004»
15 years 3 months ago
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
Elena Trichina, Tymur Korkishko, Kyung-Hee Lee
ISLPED
2000
ACM
111views Hardware» more  ISLPED 2000»
15 years 1 months ago
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
Khurram Muhammad, Robert B. Staszewski, Poras T. B...