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» Design and implementation of a low-power workstation
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ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 3 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
ICCD
2006
IEEE
121views Hardware» more  ICCD 2006»
15 years 6 months ago
A Low Power Highly Associative Cache for Embedded Systems
—Reducing energy consumption is an important issue for battery powered embedded computing systems. Content Addressable Memory (CAM)-based Highly-Associative Caches (HAC) are wide...
Chuanjun Zhang
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
15 years 3 months ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
DAC
2005
ACM
15 years 10 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
15 years 10 months ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi