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» Design and implementation of a network simulation system
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ISPASS
2009
IEEE
15 years 11 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
WSC
2004
15 years 6 months ago
Simulating Growth Dynamics in Complex Adaptive Supply Networks
This paper discusses an extended adaptive supply network simulation model that explicitly captures growth (in terms of change in size over time, and birth and death) based on Utte...
Surya Dev Pathak, David M. Dilts, Gautam Biswas
ICSEA
2006
IEEE
15 years 11 months ago
Extracting Simulation Models from Complex Embedded Real-Time Systems
A modeling process is presented for extracting timingaccurate simulation models from complex embedded realtime systems. The process is supported by two complementary methods for t...
Johan Andersson, Joel Huselius, Christer Norstr&ou...
CODES
2009
IEEE
15 years 11 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
15 years 11 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...