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» Design and implementation of correlating caches
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ICSM
2007
IEEE
15 years 3 months ago
Evaluation of Semantic Interference Detection in Parallel Changes: an Exploratory Experiment
Parallel developments are becoming increasingly prevalent in the building and evolution of large-scale software systems. Our previous studies of a large industrial project showed ...
Danhua Shao, Sarfraz Khurshid, Dewayne E. Perry
116
Voted
DAC
2004
ACM
15 years 10 months ago
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. Th...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
106
Voted
DAC
2006
ACM
15 years 10 months ago
High-level power management of embedded systems with application-specific energy cost functions
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
15 years 4 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
15 years 4 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan