584 search results - page 109 / 117 » Design and implementation of correlating caches |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...
CF
2009
ACM
15 years 4 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
81
Voted
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
71
Voted
NOMS
2006
IEEE
15 years 3 months ago
2006
IEEE
— Flow-level traffic measurement is required for a wide range of applications including accounting, network planning and security management. A key design challenge is how to gr...