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» Design and implementation of correlating caches
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81
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 11 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
SAC
2008
ACM
14 years 9 months ago
Design pattern detection by template matching
In this paper, we adopt a template matching method to detect design patterns from a software system by calculating their normalized cross correlation. Because design patterns docu...
Jing Dong, Yongtao Sun, Yajing Zhao
IESS
2009
Springer
182views Hardware» more  IESS 2009»
14 years 7 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
66
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ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
15 years 6 months ago
Energy Characterization of Hardware-Based Data Prefetching
This paper evaluates several hardware-based data prefetching techniques from an energy perspective, and explores their energy/performance tradeoffs. We present detailed simulation...
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Kri...
ASPLOS
1992
ACM
15 years 1 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta