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» Design and implementation of correlating caches
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2010
ACM
14 years 7 months ago
Design, implementation, and evaluation of an approach for determining when programmers are having difficulty
Previous research has motivated the idea of automatically determining when programmers are having difficulty, provided an initial algorithm (unimplemented in an actual system), an...
Jason Carter, Prasun Dewan
ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
15 years 1 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
CN
2002
77views more  CN 2002»
14 years 9 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...
FPL
2010
Springer
124views Hardware» more  FPL 2010»
14 years 7 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
86
Voted
CAL
2002
14 years 9 months ago
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...