Sciweavers

584 search results - page 27 / 117
» Design and implementation of correlating caches
Sort
View
84
Voted
NIPS
2001
14 years 11 months ago
Learning Spike-Based Correlations and Conditional Probabilities in Silicon
We have designed and fabricated a VLSI synapse that can learn a conditional probability or correlation between spike-based inputs and feedback signals. The synapse is low power, c...
Aaron P. Shon, David Hsu, Chris Diorio
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
15 years 4 months ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri
COMCOM
2007
149views more  COMCOM 2007»
14 years 9 months ago
Cache invalidation strategies for internet-based mobile ad hoc networks
Internet-based mobile ad hoc network (IMANET) combines a mobile ad hoc network (MANET) and the Internet to provide universal information accessibility. Although caching frequently...
Sunho Lim, Wang-Chien Lee, Guohong Cao, Chita R. D...
EUROSYS
2011
ACM
14 years 1 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
SACRYPT
2007
Springer
141views Cryptology» more  SACRYPT 2007»
15 years 3 months ago
Analysis of Countermeasures Against Access Driven Cache Attacks on AES
Cache attacks on implementations of cryptographic algorithms have turned out to be very powerful. Progress in processor design, e.g., like hyperthreading, requires to adapt models ...
Johannes Blömer, Volker Krummel