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» Design and implementation of correlating caches
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85
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CASES
2008
ACM
14 years 11 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
ICSE
2000
IEEE-ACM
15 years 1 months ago
Dragonfly: linking conceptual and implementation architectures of multiuser interactive systems
Software architecture styles for developing multiuser applications are usually defined at a conceptual level, abstracting such low-level issues of distributed implementation as co...
Gary E. Anderson, T. C. Nicholas Graham, Timothy N...
69
Voted
IPPS
2006
IEEE
15 years 3 months ago
Linyphi: an IPv6-compatible implementation of SSR
Scalable Source Routing (SSR) is a self-organizing routing protocol designed for supporting peer-to-peer applications. It is especially suited for networks that do not have a well...
Pengfei Di, Massimiliano Marcon, Thomas Fuhrmann
DSD
2002
IEEE
73views Hardware» more  DSD 2002»
15 years 2 months ago
Implementation of a Streaming Execution Unit
The Complex Streamed Instruction (CSI) set is an instruction set extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in mem...
Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vass...
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
15 years 2 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov