584 search results - page 41 / 117 » Design and implementation of correlating caches |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
82
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
100
click to vote
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
104
click to vote
MOBIDE
1999
ACM
15 years 2 months ago
1999
ACM
This paper describes the design of a system that significantly improves the performance of telnet data delivery for 3270 and 5250 emulation so that access to legacy applications v...
ICC
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper we present an alternative separable implementation of L2 -orthogonal space-time codes (STC) for continuous phase modulation (CPM). In this approach, we split the STC...