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» Design and implementation of correlating caches
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TON
2008
124views more  TON 2008»
14 years 9 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
85
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
OTM
2007
Springer
15 years 3 months ago
Invasive Patterns for Distributed Programs
Software patterns have evolved into a commonly used means to design and implement software systems. Programming patterns, architecture and design patterns have been quite successfu...
Luis Daniel Benavides Navarro, Mario Südholt,...
INFOCOM
2002
IEEE
15 years 2 months ago
Design and Scalability of NLS, a Scalable Naming and Location Service
This paper sketches the design, and presents a scalability analysis and evaluation of NLS, a scalable naming and location service. NLS resolves textual names to the nearest of a s...
Y. Charlie Hu, Daniel Rodney, Peter Druschel
LCTRTS
2007
Springer
15 years 3 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...