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» Design and implementation of correlating caches
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85
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ICPP
2008
IEEE
15 years 4 months ago
On the Design of Fast Pseudo-Random Number Generators for the Cell Broadband Engine and an Application to Risk Analysis
Numerical simulations in computational physics, biology, and finance, often require the use of high quality and efficient parallel random number generators. We design and optimi...
David A. Bader, Aparna Chandramowlishwaran, Virat ...
AES
2004
Springer
190views Cryptology» more  AES 2004»
15 years 3 months ago
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
Elena Trichina, Tymur Korkishko, Kyung-Hee Lee
BMCBI
2007
226views more  BMCBI 2007»
14 years 9 months ago
MiRFinder: an improved approach and software implementation for genome-wide fast microRNA precursor scans
Background: MicroRNAs (miRNAs) are recognized as one of the most important families of noncoding RNAs that serve as important sequence-specific post-transcriptional regulators of ...
Ting-Hua Huang, Bin Fan, Max F. Rothschild, Zhi-Li...
88
Voted
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 3 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
MICRO
1993
IEEE
97views Hardware» more  MICRO 1993»
15 years 1 months ago
Register renaming and dynamic speculation: an alternative approach
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
Mayan Moudgill, Keshav Pingali, Stamatis Vassiliad...