584 search results - page 56 / 117 » Design and implementation of correlating caches |
171
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
153
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FPL
2005
Springer
15 years 11 months ago
2005
Springer
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, Imaging, or MultiMedia) written in a subset of Matl...
173
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USENIX
1996
15 years 7 months ago
1996
This paper describes a new method for providingtransparent fault tolerance for parallel applications on a network of workstations. We have designed our method in the context of sh...
156
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
164
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ANCS
2009
ACM
15 years 3 months ago
2009
ACM
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...