584 search results - page 61 / 117 » Design and implementation of correlating caches |
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
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ISPDC
2010
IEEE
14 years 8 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
MOBISYS
2005
ACM
15 years 9 months ago
2005
ACM
Energy efficiency has become a critical issue for battery-driven computers. Significant work has been devoted to improving it through better software and hardware. However, the hu...
MSWIM
2004
ACM
15 years 3 months ago
2004
ACM
Emerging “urban” ad hoc networks resulting from a large number of individual WLAN users challenge the way users could explore and interact with their physical surroundings. Ro...
MICRO
2002
IEEE
14 years 9 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...