584 search results - page 62 / 117 » Design and implementation of correlating caches |
HPCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
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PASTE
2010
ACM
15 years 2 months ago
2010
ACM
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
FPL
2007
Springer
15 years 3 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
ICAC
2006
IEEE
15 years 3 months ago
2006
IEEE
Grid data management is a challenging task because of the heterogeneous, dynamic and largescale nature of Grid environments. This paper proposes an autonomic Grid data management ...