Sciweavers

584 search results - page 73 / 117
» Design and implementation of correlating caches
Sort
View
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 4 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
HPDC
2008
IEEE
15 years 4 months ago
Combining batch execution and leasing using virtual machines
As cluster computers are used for a wider range of applications, we encounter the need to deliver resources at particular times, to meet particular deadlines, and/or at the same t...
Borja Sotomayor, Kate Keahey, Ian T. Foster
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
15 years 3 months ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt
CODES
2009
IEEE
15 years 1 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...
CLADE
2004
IEEE
15 years 1 months ago
Engineering a Peer-to-Peer Collaboratory for Tissue Microarray Research
This paper presents the design, development and evaluation of a prototype peer-to-peer collaboratory for imaging, analyzing, and seamlessly sharing tissue microarrays (TMA), corre...
Cristina Schmidt, Manish Parashar, Wenjin Chen, Da...