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» Design and implementation of correlating caches
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SIGSOFT
2007
ACM
15 years 10 months ago
Program comprehension as fact finding
Little is known about how developers think about design during code modification tasks or how experienced developers' design knowledge helps them work more effectively. We pe...
Thomas D. LaToza, David Garlan, James D. Herbsleb,...
VLSISP
2011
358views Database» more  VLSISP 2011»
14 years 4 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
OOPSLA
2009
Springer
15 years 4 months ago
A concurrent dynamic analysis framework for multicore hardware
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
Jungwoo Ha, Matthew Arnold, Stephen M. Blackburn, ...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 1 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
15 years 1 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha