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» Design and implementation of correlating caches
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SIGCOMM
2009
ACM
15 years 4 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
15 years 2 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
15 years 6 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
14 years 11 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
77
Voted
TIP
1998
125views more  TIP 1998»
14 years 9 months ago
Additive vector decoding of transform coded images
—In a standard transform coding scheme of images or video, the decoder can be implemented by a table-lookup technique without the explicit use of an inverse transformation. In th...
Siu-Wai Wu, Allen Gersho