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» Design and implementation of correlating caches
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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 2 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
ICS
2009
Tsinghua U.
15 years 2 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
HPCA
1998
IEEE
15 years 1 months ago
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
Sujoy Basu, Josep Torrellas
MATA
2000
Springer
137views Communications» more  MATA 2000»
15 years 1 months ago
Topology Discovery in Ad Hoc Wireless Networks Using Mobile Agents
Extensive research on mobile agents has been rife with the growing interests in network computing. In this paper, we have discussed a mobile multi-agent-based framework to address ...
Romit Roy Choudhury, Somprakash Bandyopadhyay, Kri...
CORR
2010
Springer
91views Education» more  CORR 2010»
14 years 4 months ago
TSDS: high-performance merge, subset, and filter software for time series-like data
Time Series Data Server (TSDS) is a software package for implementing a server that provides fast supersetting, sub-setting, filtering, and uniform gridding of time series-like dat...
Robert S. Weigel, Doug M. Lindholm, A. Wilson, Jer...