Sciweavers

3116 search results - page 69 / 624
» Design and implementation of network puzzles
Sort
View
CANPC
1999
Springer
15 years 4 months ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
FLAIRS
2003
15 years 1 months ago
Advantages of Brahms for Specifying and Implementing a Multiagent Human-Robotic Exploration System
We have developed a model-based, distributed architecture that integrates diverse components in a system designed for lunar and planetary surface operations: an astronaut’s spac...
William J. Clancey, Maarten Sierhuis, Charis Kaski...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 6 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
IJRR
2010
173views more  IJRR 2010»
14 years 10 months ago
Planning and Implementing Trajectories for Autonomous Underwater Vehicles to Track Evolving Ocean Processes Based on Predictions
Path planning and trajectory design for autonomous underwater vehicles (AUVs) is of great importance to the oceanographic research community because automated data collection is b...
Ryan N. Smith, Yi Chao, Peggy Li, David A. Caron, ...
74
Voted
HPCA
2009
IEEE
16 years 13 days ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...