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» Design and implementation of network puzzles
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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
15 years 6 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
DAC
2001
ACM
16 years 26 days ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles
NSDI
2008
15 years 2 months ago
UsenetDHT: A Low-Overhead Design for Usenet
Usenet is a popular distributed messaging and file sharing service: servers in Usenet flood articles over an overlay network to fully replicate articles across all servers. Howeve...
Emil Sit, Robert Morris, M. Frans Kaashoek
FGCS
2002
153views more  FGCS 2002»
14 years 11 months ago
HARNESS fault tolerant MPI design, usage and performance issues
Initial versions of MPI were designed to work efficiently on multi-processors which had very little job control and thus static process models. Subsequently forcing them to suppor...
Graham E. Fagg, Jack Dongarra
SIGCOMM
2009
ACM
15 years 6 months ago
Building a fast, virtualized data plane with programmable hardware
Network virtualization allows many networks to share the same underlying physical topology; this technology has offered promise both for experimentation and for hosting multiple n...
Muhammad Bilal Anwer, Nick Feamster