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113
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ICIP
1995
IEEE
16 years 5 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C...
ISCAS
2007
IEEE
135views Hardware» more  ISCAS 2007»
15 years 10 months ago
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
Ming-Dou Ker, Hung-Tai Liao
CASES
2008
ACM
15 years 5 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
108
Voted
EUROSYS
2010
ACM
16 years 25 days ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
DAC
2008
ACM
16 years 4 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin