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CASES
2009
ACM
15 years 7 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
130
Voted
COMPSAC
2009
IEEE
15 years 10 months ago
A Perspective on Middleware-Oriented Context-Aware Pervasive Systems
The evolving concepts of mobile computing, context-awareness, and ambient intelligence are increasingly influencing user's experience of services. Therefore, the goal of this...
Zakwan Jaroucheh, Xiaodong Liu, Sally Smith
GLOBECOM
2007
IEEE
15 years 10 months ago
Design of High Throughput Scheduled Mesh Networks: A Case for Directional Antennas
Abstract— Scheduled wireless mesh networks (WMNs) represent an important paradigm in the development of high speed wireless access networks. As a consequence of [1], it can be sh...
Skanda N. Muthaiah, Aravind Iyer, Aditya Karnik, C...
AIMS
2008
Springer
15 years 10 months ago
A Theory of Closure Operators
We explore how fixed-point operators can be designed to interact and be composed to form autonomic control mechanisms. We depart from the idea that an operator is idempotent only ...
Alva L. Couch, Marc Chiarini
106
Voted
SLIP
2003
ACM
15 years 8 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...