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113
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EH
1999
IEEE
122views Hardware» more  EH 1999»
15 years 8 months ago
The MorphoSys Dynamically Reconfigurable System-on-Chip
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Ba...
ICSEA
2007
IEEE
15 years 10 months ago
An Extensible Architecture for Network-Attached Device Management
The development of network-attached devices has ushered in an era of autonomous, multi-function equipment demanding minimal human interaction: the only requirements are data and e...
Michael J. McMahon Jr., Sergiu M. Dascalu, Frederi...
CF
2008
ACM
15 years 5 months ago
Fpga-based prototype of a pram-on-chip processor
PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel machine model for many years, but it is also believed to be "impossible in reality." As...
Xingzhi Wen, Uzi Vishkin
126
Voted
RTSS
2006
IEEE
15 years 9 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
147
Voted
VTC
2010
IEEE
242views Communications» more  VTC 2010»
15 years 2 months ago
A Cross-Layer Design Based on Geographic Information for Cooperative Wireless Networks
—Most of geographic routing approaches in wireless ad hoc and sensor networks do not take into consideration the medium access control (MAC) and physical layers when designing a ...
Teck Aguilar, Mohamed Chedly Ghedira, Syue-Ju Syue...