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» Design for Verification of SystemC Transaction Level Models
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CODES
2006
IEEE
15 years 3 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
ACSC
2009
IEEE
15 years 1 months ago
Verification of the SIP Transaction Using Coloured Petri Nets
The Session Initiation Protocol (SIP) is one of the leading protocols for multimedia control over the Internet, including initiating, maintaining and terminating multimedia sessio...
Lin Liu
FMICS
2006
Springer
15 years 1 months ago
Test Coverage for Loose Timing Annotations
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
Claude Helmstetter, Florence Maraninchi, Laurent M...
DSD
2009
IEEE
93views Hardware» more  DSD 2009»
14 years 7 months ago
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
Antonio da Silva, Sebastian Sanchez
CODES
2003
IEEE
15 years 3 months ago
Transaction level modeling: an overview
Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the us...
Lukai Cai, Daniel Gajski