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» Design for Verification of SystemC Transaction Level Models
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EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
15 years 6 months ago
Fast and accurate transaction level models using result oriented modeling
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
Gunar Schirner, Rainer Dömer
TCAD
2008
75views more  TCAD 2008»
14 years 9 months ago
Static Analysis of Transaction-Level Communication Models
We propose a methodology for the early estimation of communication implementation choices eftarting from an abstract transaction level system model (TLM). The reference version of ...
Giovanni Agosta, Francesco Bruschi, Donatella Sciu...
IEICET
2006
114views more  IEICET 2006»
14 years 9 months ago
Synchronization Verification in System-Level Design with ILP Solvers
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro ...
RTCSA
2007
IEEE
15 years 4 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...