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» Design for Verification of SystemC Transaction Level Models
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TECS
2008
122views more  TECS 2008»
14 years 9 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
DAC
2006
ACM
15 years 3 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
15 years 3 months ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer
ICSE
2004
IEEE-ACM
15 years 9 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
JCP
2008
142views more  JCP 2008»
14 years 9 months ago
Design and Verification of Loosely Coupled Inter-Organizational Workflows with Multi-Level Security
Inter-Organizational Workflows (IOWF) become important as they provide solution for data sharing, heterogeneity in resources and work coordination at global level. However, a secur...
Boleslaw Mikolajczak, Nirmal Gami