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» Design for Verification of SystemC Transaction Level Models
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MASCOTS
2000
14 years 11 months ago
A Transaction-Level Tool for Predicting TCP Performance and for Network Engineering
Most network engineering tools are unsatisfactory. Measurements are not predictive, simulations do not scale, and analysis is limited to oversimplified models. To be more useful, ...
Jean C. Walrand
RTCSA
2005
IEEE
15 years 3 months ago
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, We...
WISE
2002
Springer
15 years 2 months ago
UTML: Unified Transaction Modeling Language
Web transactions may be complex, composed of several sub-transactions accessing different resources including legacy systems. They may also have complex semantics. To deal with co...
Nektarios Gioldasis, Stavros Christodoulakis
CODES
2005
IEEE
15 years 3 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 1 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...