275 search results - page 20 / 55 » Design for Verification of SystemC Transaction Level Models |
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
CORR
2007
Springer
14 years 9 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
176
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ICDE
2006
IEEE
15 years 11 months ago
2006
IEEE
Scheduling/prioritization of DBMS transactions is important for many applications that rely on database backends. A convenient way to achieve scheduling is to limit the number of ...
DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
116
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DAC
2002
ACM
15 years 10 months ago
2002
ACM
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...