275 search results - page 23 / 55 » Design for Verification of SystemC Transaction Level Models |
DAC
1997
ACM
15 years 1 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
FMAM
2010
14 years 7 months ago
2010
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
FMCAD
2006
Springer
15 years 1 months ago
2006
Springer
In this paper we formally specify and verify an implementation of the IEEE802.11a standard physical layer based OFDM (Orthogonal Frequency Division Multiplexing) modem using the HO...
105
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FDL
2006
IEEE
15 years 3 months ago
2006
IEEE
Reusing IP-cores to construct system models facilitated by automated generation of glue-logic, and automated composability checks can help designers to create efficient simulation...
TC
1998
14 years 9 months ago
1998
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...