275 search results - page 26 / 55 » Design for Verification of SystemC Transaction Level Models |
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
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EUROMICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
APCCM
2008
14 years 11 months ago
2008
The work presented in this paper targets the software integration on the level of business process models. The goal is to create the behavioural description of an integrated syste...
TCAD
2008
14 years 9 months ago
2008
Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task...