275 search results - page 27 / 55 » Design for Verification of SystemC Transaction Level Models |
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CODES
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
ISLPED
2009
ACM
15 years 4 months ago
2009
ACM
In an interactive embedded system, special task execution patterns and scheduling constraints exist due to frequent human-computer interactions. This paper proposes a transaction-...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
ASYNC
1997
IEEE
15 years 1 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
ASE
2008
14 years 10 months ago
2008
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...